Generally, electronic design automation (EDA) tools assist semiconductor designers to take a purely behavioral description of a desired circuit and work to fashion a finished layout of the circuit ready to be manufactured. This process usually takes the behavioral description of the circuit and turns it into a functional description, which is then decomposed into thousands of Boolean functions and mapped into rows of cells using a standard cell library. Once mapped, a synthesis is performed to turn the structural design into a physical layout, a clock tree is built to synchronize the structural elements, and the design is optimized post layout.
Generally, in order to avoid problems with aligning the cells from the library with common power rails or other design rules, a standardized cell from a cell library is used which has either a cell height equal to the height of the cell row or else has a cell height that is a multiple of the standard cell height. As such, typically a decision is made early on as to which cell height to utilize for the design, and the cell library corresponding to that cell height is used for the structural design and synthesis processes.
However, by using only a single cell height, some compromises between circuit performance, circuit power, and the manufacturing process must be made. For example, cells with a low threshold voltage have relatively high speed and power but, also require an extra masking step during manufacturing. Alternatively, cells with a relatively high threshold voltage design may use a lower amount of power, but also has a low speed when compared to the low threshold voltage, while still requiring an extra mask. Compromise cell sizes, which would give a threshold voltage between the low threshold voltage and the high threshold voltage, merely split the differences, supplying a medium speed and a medium power, but not requiring an extra mask. As such, these compromises limit the performance, power, and manufacturing options that may otherwise be used to design smaller, faster, and more power efficient designs.